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      <title>Article: Engineering Speed at Scale — Architectural Lessons from Sub-100-ms APIs</title>
      <link>https://www.infoq.com/articles/engineering-speed-scale/?utm_campaign=infoq_content&amp;utm_source=infoq&amp;utm_medium=feed&amp;utm_term=Low+Latency-articles</link>
      <description>&lt;img src="https://res.infoq.com/articles/engineering-speed-scale/en/headerimage/engineering-speed-scale-header-1767006608903.jpg"/&gt;&lt;p&gt;Sub‑100-ms APIs emerge from disciplined architecture using latency budgets, minimized hops, async fan‑out, layered caching, circuit breakers, and strong observability. But long‑term speed depends on culture, with teams owning p99, monitoring drift, managing thread pools, and treating performance as a shared, continuous responsibility.&lt;/p&gt; &lt;i&gt;By Saranya Vedagiri&lt;/i&gt;</description>
      <category>Low Latency</category>
      <category>Performance Tuning</category>
      <category>Performance</category>
      <category>Architecture &amp; Design</category>
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      <pubDate>Thu, 29 Jan 2026 16:00:00 GMT</pubDate>
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      <dc:creator>Saranya Vedagiri</dc:creator>
      <dc:date>2026-01-29T16:00:00Z</dc:date>
      <dc:identifier>/articles/engineering-speed-scale/en</dc:identifier>
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